1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory having nonvolatile memory cells.
2. Description of the Related Art
Nonvolatile semiconductor memories such as flash memories store data by holding or not holding electrons in the floating gates or trap gates of memory cell transistors (hereinafter also referred to as “memory cells”). For example, in a nonvolatile semiconductor memory disclosed in Japanese Unexamined Patent Application Publication No. 7-114796, memory cells are formed at the intersecting points of word lines and bit lines which are perpendicular to each other. Source lines which are connected to the sources of the memory cells are arranged parallel with the word lines. The sources of memory cells that are arranged along a pair of word lines are connected to a common source line. The drains of memory cells that are arranged parallel with the bit lines are connected to a common bit line.
Japanese Unexamined Patent Application Publication No. 8-69696 discloses a technique which makes it possible to continuously read data from memory cells even at the time of word line switching by accessing two memory cell arrays (subarrays) alternately.
In the nonvolatile semiconductor memory of Japanese Unexamined Patent Application Publication No. 7-114796, memory cells that are connected to adjoining word lines and arranged parallel with the bit lines are connected to a common bit line and a common source line. In performing reading on these memory cells, selection periods of the adjoining word lines are not allowed to overlap with each other. Therefore, where addresses are supplied randomly (random access) in read operations, data cannot be output continuously from the memory cells. In the technique of Japanese Unexamined Patent Application Publication No. 8-69696, random access is possible only when the subarrays are accessed alternately. That is, where random access is performed on one subarray, data cannot be output continuously. In particular, random access cannot be performed in nonvolatile semiconductor memories in which parallel processing (pipeline processing) is performed by overlapping a part of activation periods of word lines in read operations.